This invention is in the field of simulation of integrated circuits, and is more specifically directed to the simulation of integrated circuits including polarizable ferroelectric capacitors.
Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly portable electronic devices and systems. A recently developed technology for realizing non-volatile solid-state memory devices is commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM”. According to this technology, memory cells are realized as capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-vs.-voltage (Q-V) characteristic based on the polarization state of the ferroelectric material, enables the non-volatile storage of information in the FRAM cell. In contrast, conventional dynamic random access memory (DRAM) memories are volatile, because DRAM memory cells use MOS capacitors, with conventional silicon dioxide or silicon nitride dielectrics, that lose their stored charge on power-down of the device.
FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage Vα, the capacitor is polarized into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor will exhibit a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα. Conventional FRAM devices commonly “read” the polarization state of the ferroelectric capacitor in each memory cell by causing a state change, and sensing whether current is output by the capacitor in response. For example, if the capacitor is already in a “+1” polarization state, no current will be output by applying a read voltage above coercive voltage Vα; conversely, if the capacitor is in the “−1” polarization state, a current pulse will be produced as the capacitor changes state. This conventional read approach is thus a destructive process, requiring rewriting of the memory cell to replace the previous data state. Recent approaches have been developed that non-destructively read the polarization state of the device.
Simulation of the operation of electronic circuits is a staple task in the design of integrated circuits, even for the most simple of functions but especially as integrated circuit functionality and thus complexity has increased over time. Modern circuit simulation tools not only allow the circuit designer to ensure that the circuit carries out the intended function, but also enable the designer to evaluate the robustness of circuit operation over variations in temperature, signal levels, power supply voltages, and process parameters. A well-known circuit simulation program is the Simulation Program with Integrated Circuit Emphasis, commonly referred to as SPICE, originated at the Electronics Research Laboratory of the University of California, Berkeley. Many commercial versions of the SPICE program are now available in the industry, including several versions that are internal or proprietary to integrated circuit manufacturers.
According to SPICE-based circuit simulators, the circuit being simulated is expressed in terms of its elements such as resistors, transistors, capacitors, and the like. Each circuit element is associated with a model of its behavior (i.e., response to voltage or current stimuli), and is “connected” into the overall circuit simulation by specifying the circuit nodes to which it is connected. DC, AC, or transient analysis of the circuit is then performed by specifying any initial conditions (voltages, currents, stored charge etc.), as well as the variable or node of interest, for which the circuit response is to be analyzed. Higher level analysis of the circuit, for example noise analysis, transfer functions, and the like, can also be performed via such simulation.
The models used for semiconductor devices in the simulation can be relative simple circuit-based models, for example corresponding to the well-known Ebers-Moll or Gummel-Poon models. However, models based on device physics have now been derived that determine the device electrical characteristics according to physical parameters such as channel width, channel length, film or layer thicknesses, proximity to other devices, and the like. Such physical models can be correlated or combined with complex empirical electrical models derived from curve fitting to actual device electrical measurements, further improving (at least in theory) the precision with which the behavior of the circuit element can be simulated.
Typically, those device models that are defined largely by device physics parameters are especially useful in “analog” simulation of specific circuit functions, such as sense amplifiers. Other simulations, such as logic simulation of larger functions in the integrated circuit, typically do not require the precision of complex physical and empirical device models.
Examples of conventional models of ferroelectric capacitor behavior are described in Sheikholeslami et al., “A Survey of Behavioral Modeling of Ferroelectric Capacitors”, Trans. Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 44, No. 4 (IEEE, July 1997), pp. 917-24. Many of these conventional models are directed to models of the behavior of the “saturation” loop, which is generally considered as the switching component of the largest hysteresis loop of the ferroelectric capacitor. FIG. 1 shows such a saturation loop. As known in the art, the ferroelectric material between plates of the capacitor physically includes multiple polarization “domains”, analogous to magnetic domains in ferromagnetic material. A domain is a homogenous region of a ferroelectric, in which all of the dipole moments in adjacent unit cells have the same orientation. The saturation loop is thus the Q-V hysteresis characteristic that describes the polarization of all of the ferroelectric domains within the capacitor in the same direction. As described in the Sheikholeslami et al. article, a hyperbolic tangent (tan h) function is a good approximation for the shape of the transition regions of the saturation loop.
By way of further background, the “distributed threshold switching model” described in the Sheikholeslami et al. article models ferroelectric capacitor polarization behavior over a large number of dipole domains. More specifically, this approach uses a Gaussian distribution of polarization over these domains, with the coercive voltage Vc characterized by a mean value and standard deviation. From a circuit standpoint, this model treats the ferroelectric capacitance as five parallel circuit elements, including one resistor, one linear capacitor, and three non-linear capacitors. One of the non-linear capacitors represents the switching polarization of the ferroelectric capacitor, and is modeled by two Gaussian distributions of polarization versus voltage, representative of the multiple domains. One of the Gaussian distributions has a mean at the positive coercive voltage +Vα to the “+1” state, while the other has a mean at the negative coercive voltage Vβ to the “−1” state. The extent to which domains are polarized by a positive transition of a modeled applied voltage is defined by the Gaussian distribution of the positive coercive voltage Vα.
By way of further background, Jiang et al., “Computationally Efficient Ferroelectric Capacitor Model for Circuit Simulation”, Digest of Technical Papers, Symposium on VLSI Technology, Paper 10B-4 (IEEE, 1997), pp. 141-42, describes a multi-domain ferroelectric capacitor model that accounts for the history dependence of polarization for applied voltage levels below the coercive voltages. As known in the art, applied voltages below the coercive voltages tend to reduce the overall polarization of the capacitor. According to this model, the outer saturation loops are approximated by way of a tan h function of applied voltage, as in the Sheikholeslami et al. article. If lower magnitude voltages, between the coercive voltages, are then applied to the capacitor, some but not all of the domains will switch their polarization to the opposite state, and the overall Q-V characteristic changes accordingly. In short, the amount of charge stored by the remanent polarization in the device is reduced. According to the Jiang et al. approach, the history of these lower applied voltages applied to the capacitor is modeled by transformation of the tan h approximation of the outer saturation loops to define minor polarization loops lying within the outer saturation loop. More specifically, the Jiang et al. model identifies “turning points” in the Q-V characteristic over time, corresponding to changes in direction (i.e., changes in sign of dV/dt). The Q-V minor loop connecting two turning points is then defined by calculating a slope and intercept by way of which the outer saturation loop tan h function can fit the two turning points. As a result, the minor loops maintain the tan h shape, but fit the initial conditions at the turning points.
As known in the art, ferroelectric capacitors are vulnerable to various physical degradation mechanisms that appear as undesirable changes in the Q-V characteristics of the capacitors. While the electrical behavior of ferroelectric capacitors is complicated to model even without these degradation effects, as evident from conventional SPICE-related models such as described in the Sheikholeslami et al. and Jiang et al. articles, it is especially difficult to model that complex electrical behavior as it degrades over time and voltage history. The models described in the Sheikholeslami et al. and Jiang et al. articles in fact do not address time-dependent or stress-dependent effects.
One of these degradation mechanisms, referred to in the art as relaxation, is the loss of polarization over time in the absence of an applied external field. FIG. 2a illustrates the effect of relaxation on an example of a ferroelectric capacitor, by way of curves 2+ and 2−, illustrating the loss of polarization from the “+1” and “−1” states, respectively. The loss of polarization due to the relaxation mechanism appears as a loss of stored charge by the capacitor. For example, a ferroelectric capacitor polarized to a “+1” state but that undergoes relaxation under the absence of bias, for a sufficient time, can lose polarization and thus stored charge by an amount ΔP between the full “+1” state and curve 2+. Curve 2− shows the effect of relaxation from the “−1” polarization states. Typically, the coercive voltages Vα and Vβ do not typically shift due to relaxation, to any substantial extent. The loss of polarization due to relaxation in FRAM memory cells increases the likelihood of a read error, because the loss of charge is reflected directly in a reduction in the output current from the cell.
Another degradation mechanism is referred to in the art as “imprint”, which is an “end-of-life” mechanism for ferroelectric devices. In contrast to the effects of relaxation generally disappear upon repolarization of the capacitor, imprint is exhibited by permanent shifts in the shape of the hysteresis loop, generally appearing as flattened slopes in the transition curves and shifting in the polarization charge levels that result in an overall loss of area within the hysteresis loop. One type of imprint, referred to as “dynamic” imprint, results from repetitive or extended application of voltage exceeding one of the coercive voltages Vα or Vβ, as the case may be, which effectively rewrites the same data in the cell. Imprint of the static type refers to permanent shifts in the polarization characteristic due to the capacitor remaining in one polarization state over time without external bias. FIG. 2b illustrates the effect of imprint on the Q-V characteristic of an example of a ferroelectric capacitor, by way of shifted characteristic curve 4. In this somewhat extreme case, the effects of imprint include inadequate polarization of the capacitor in either state, as well as poorly defined coercive voltages. Not only does imprint result in data storage errors for ferroelectric capacitors used as FRAM memory cells, but the effects of imprint also disrupt the small signal behavior of ferroelectric capacitors that may be implemented as capacitors in analog circuits and the like.
Rigorous simulation of integrated circuits including ferroelectric devices necessitates consideration of the effects of relaxation and imprint. For example, proper consideration of relaxation and imprint is appropriate in designing sense amplifiers with sufficient margin for ferroelectric capacitors that have lost polarization due to relaxation or imprint. In the SPICE model context, therefore, it is useful to derive ferroelectric capacitor models that are responsive to time and voltage histories of the capacitor in producing Q-V models that can accurately predict the behavior of actual devices as a result of these effects.
By way of further background, Kühn et al., “A New Physical Model for the Relaxation in Ferroelectrics”, Proceedings of the 30th European Solid-State Device Research Conference (IEEE, 2000), pp. 164-67, describes the inclusion of relaxation effects into the Jiang et al. model. More specifically, the Kühn et al. article describes the calculation of artificial turning points that are a function of elapsed waiting time. These turning points are used to define additional minor loops in the Q-V characteristic, again by calculating a slope and intercept so that the tan h approximations of the outer saturation loops are fit to the artificial turning points and thus define the minor loops.
It has been observed, in connection with this invention, that the treatment of relaxation and imprint effects by conventional ferroelectric capacitor models are limited in their accuracy, relative to the stringent demands of modern integrated circuit design requirements. For example, while the Kühn et al. article describes a model for relaxation effects, that approach is constrained to a model in which the minor loops necessarily have a tan h shape. No physical basis is presented to support the supposition that the minor loops will have such a shape after relaxation, much less correspond to changes in the saturation loop due to imprint.
Other limitations of conventional ferroelectric capacitor models that have been observed, in connection with this invention, include the limited ability of those models to match experimental data regarding the minor loops of the polarization characteristic, especially over a relatively wide range of input signals. The effects of relaxation or imprint, and of the pulse-width dependence of capacitor performance, are also not well-incorporated into conventional models.
As such, the accuracy of simulations of modern FRAM devices or large-scale logic circuits including ferroelectric memory has been limited. This inaccuracy in simulation can lead, in the worst case, to errors in the operation of the designed integrated circuit. To avoid such errors, fabrication and electrical testing of actual ferroelectric devices is necessary to validate integrated circuit design. Typically, multiple design iterations and extensive costly testing is necessary to optimize the circuit design for actual device behavior. While the prudent designer, aware of the limitations of the FRAM model, can avoid circuit failure by designing sufficient operating margin into the circuit, such design overkill will not have optimum performance or efficiency, and can be unnecessarily costly in integrated circuit chip area.